In semiconductor chips, power lines and ground lines are routed to logic gates in integrated circuits. The current from power supply flows through power lines, logic gates, and finally to ground. During the switching of the logic gates, a large amount of change in the current occurs within a short period of time. Decoupling capacitors are used to absorb these glitches during current switching and to maintain a constant voltage between supply voltage and ground. Good decoupling capacitors should show high capacitance per unit area, low leakage current and short time constant.
One such decoupling capacitor known in the art is the area Metal-Insulator-Metal (MiM) capacitor. A MiM capacitor comprises two conductive metal layers and a dielectric insulator layer. The capacitance is formed between these two conductive metal layers. MiM capacitors can achieve both high unit capacitance and fast time constant. But, as integrated circuits shrink, dielectric reliability, as measured by, for example, time-dependent dielectric breakdown or TDDB, becomes a concern. The power line signal voltage has approached the maximum allowable stress voltage for the MiM decoupling capacitor, discouraging the use of MiM capacitors in decoupling circuits.
Desirable in the art is an improved decoupling capacitor design that would improve upon the conventional capacitor designs.